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IMPORTANT QUESTIONS
PART-B (7 MARKS OR 14 MARKS)
UNIT-1
1. Draw the logic gates using NMOS & CMOS**
2. Draw the NOT gate using CMOS explain.
3. Explain the steps involved in VLSI design process.**
4. Draw the NAND gate using NMOS and explain.
5. What are the different levels of abstractions in VLSI design explain.**
6. Draw the CMOS AND, OR,NOR gates inverter and explain.**
7. Explain stick diagram
8. Explain placement and routing
UNIT-2
1. Write a VHDL code for logic gates NAND, XOR, NOR (using if else & keyword)***
2. Write the syntax for 'if elseif else statement. Explain with an example.
3. Explain the different types of HDI modeling.
4. Explain structure of VHDL
5. Explain general format of VHDL
6. Explain signal, variable, component declaration
UNIT-3
1. Write a VHDL program for half subtractor with diagram.
2. Write a VHDL program for four-bit arithmetic subratetor & adder in structural model.
3. Draw block diagram circuit diagram and truth table for half adder and explain
4. Write a VHDL program for comparator with diagram.
5. Write the VHDL code for 4:2 encoder.
6. Write the VHDL code for 1:4 demux.
7. Write the VHDL code for 4:1 multiplexer.*
8. Write the VHDL, code for 4x2, 2 to 4 decoder with diagram
UNIT-4
1. Explain ring counter with diagram.
2. Write a VHDL program for D flip flop with reset and without rest input.
3. Write a VHDL program for Johnson counter.*
4. Write a VHDL code for JK flip flop with reset input and diagram **
5. Write a VHDL code for decade counter.**
6., Write a VHDL code for T-FF with reset input
7. Write a VHDL code for 3bit up counter with diagram
UNIT-5
1. Explain PAL with diagram
2. Implement the function using
f1 = (0, 1, 3, 5) f 2= (3, 5, 7) PLA
3. Illustrate how a PLA will be used for combinational logic for the following functions
F1(a, b, c) = (0, 1, 3, 4)
F2(a, b, c) = (0, 2, 3, 4, 5, 7)
F = (3, 4, 5, 7, 10, 14, 15) in PAL
4. Draw the architecture of FPGA and explain
5. Draw the architecture of CPLD and explain
6. Using PROM realize the following expression
F1(a, b, c) = (0, 1, 3, 5, 7)
F2(a, b, c) = (1, 2, 5, 6)
7. Explain steps in ASIC design flow
8. Combinational circuit is defined by F(0,2,6,7,8,9,12,13,14) PROM
***ALL THE BEST***
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